Challenges In Stacking HBM

Hi, I'm Ed Sperling. I'm the editor and chief of semiconductor engineering. I'm

over at onto innovation with Damon Sai.

We're going to talk today about challenges in stacking HBM.

Damon, how many layers are we up to now and where are they going with this in HBM? You're trying to get more density

HBM? You're trying to get more density in here, right?

>> Yeah, I think right now the HBM when we are talking about like the three or three, we are still talking about the eight layers, but I think the most industry already moved to the 12 because we are talking about the HBM 4 right

now. But as you can image people always

now. But as you can image people always asking for the more memory for the next gen the AI chips right. So actually we already see the trend to the 16 the 20 even I see some paper from the research

center they are talking about the 24 to the 2030. So my feeling is that the

the 2030. So my feeling is that the staking will become higher and higher that means that will bring the more challenge in terms of the process control for the HBN >> and this is going to get very

interesting. Let's take a closer look.

interesting. Let's take a closer look.

>> Sure.

>> Damon what are we looking at? Okay. So I

think let's just talk about the challenge when we are talking about the more stacking layer. I think especially people when we are talking about interconnect I think the quality is always come from the microbond

connection. So what is the challenge

connection. So what is the challenge when we see the more staking layer what is bring that in terms of the quality control for the interconnection. So you

can see here this is the reflow and this is a microbond. So what we see is that both the bump pitch and the bump size continue to shrink. I think in the past we are still seeing like the 20 micron

pitch and the 10 micron diameter even the 20 micron bon height but I think once we move the to even the 16 we already see the bump page less than the 10 micron and even the bong height

shrink from the 20 micron down to the less than 10 micron and actually that's been a lot of a challenge for the defense inspection >> and you've got all these mechanical issues going on here too as you start stacking these layers and the dyes

themselves are being thinned out too right >> that's correct so Because once we want to get the more stacking height actually we still need to comply with the semi uh standard right we have the limitation

for the height. So that means the dice thickness actually become similar and similar. So that means the CMP the TSV

similar. So that means the CMP the TSV all the process actually become very different especially for the diary control that is the same challenge as well.

>> You're still trying to get movement of data very quickly. I mean this is all about uh speed of response right how fast you can store it how fast you can access it but as you go through 24 layers how does that actually move are

you starting to slow it down just in the memory itself well actually I think that is a good question because in the past we keep kind of the joking we are saying that in the future we will use the AI to

enable the AI inspection but actually I think right now that is coming so because like you mentioned because with more data comp composition actually the will slow down the whole process. So

that means the original architecture actually doesn't work. I can give you one example. I remember when we are

one example. I remember when we are doing the HBN2 the data size is like the 17 millionish but right now we are talking about 100 million B. So we are talking about tons of the gigabyte data.

So in terms of the data processing I think the both the process control group also need to improve and change the architecture. So we are literally enter

architecture. So we are literally enter the era that we are using the AI architecture to enable the nextG AI inspection.

>> Is that even possible? I mean you got so much process variation, you've got warpage, you got all these things that you've never had to deal with before at this level.

>> So I think uh actually the customer always ask us what is our capability in terms of the process control. Then we

always ask back what is your uh challenge and I think the the always the answer is that we are not sure because we are still in the R&D phase. So that's

why as Anton innovation actually we are thinking about then how we can address the some challenge that the customer may not know. So our strategy actually we

not know. So our strategy actually we are thinking about to have the single platform and have the multiple different capability. So that means maybe you we

capability. So that means maybe you we can do the ABC on the same platform but in the end the customer turns out oh I only need a C then we just remain stay with the C not like we designed three

different tool but in the end they only buy one because in terms of our is not good for the supplier as well as the customer. So that's why our design

customer. So that's why our design concept is always trying to get the most of flexibility platform can suitable both R&D and HVM >> and you're talking about looking at this

from multiple different angles which is interesting because you can't really see all the pieces anymore. So now you have to work in concert with different kinds of testing as you're going along here too right?

>> Yeah, that's correct. So that's why I think uh actually I also feel like in the past a couple years our customers concept also changed because at the beginning they always thinking about oh let's just do the 1 to 10 then we decide

what but I think right now they already be more specific because I think uh during this journey not just uh our customer involved we also involved so right now we have a different engagement

uh in the past we meet like the by the quarterly base but right now we meet in the monthly base weekly base we are very tighten into their process uh development so we can shrink down the

limitation that we kind of spread out all the possibility down to the many focus and we can also get a very good hit rate. I mean hit rate means that

hit rate. I mean hit rate means that this is really address the ED issue. So

I think the circle time also improve a lot during this collaboration >> and there's a layer of logic built into this as well right and so what problems does that cause because that's going to generate some heat as well.

>> That's correct. I think the heating problem is always the challenge and I think the one of the reason why the customer also want to reduce the thickness of the silicon because we can

reduce the electrical path that means we can also reduce the thermal effect I think that's for sure but in the other side they are trying to increase the capacity for the memory that means we

have more interconnect so I think we are thinking about how we can really address that issue I think the one trend I'm seeing that is that the customers start to talking about moving into the hybrid

bonding for sure because that is the smallest way we can do right and also we are talking about the core optics packaging I think that is another way we can reduce the overall heat effect

across the all AI chip packaging as well >> what happens with hybrid bonding versus microbumps how does that change things >> I would say we are in the uh transition period because uh one way customer keep

thinking about oh hybrid bonding is much easier to reduce the effect that we just talked about but I think in the other side they also concerned about the yield because we all know the HBN when we do

the D2 D stacking it's already difficult and we are talking about a 16 and 24 so assuming only one die failed across the 500 D per wafer that might cause a 2%

ear loss right but if we do the wafer to wafer bonding then we cannot do the pick and place then the ear loss will accumulate with the uh staking layer increase that's why the customer is

worried about until they can fully control the process challenge they are they are very cautious to move from the microbond to hybrid bonding because uh they cannot do the pick and place to do the KGD anymore.

>> Does the matter of you going 8 high versus 12 high is the process still the same or is it a completely different process?

>> I would say the process still remain uh similar but I think that people start to think about a concept we so called the hybrid hybrid bonding. So what is that means that for example when we said a height so we are always using the

microbump but the customer start to think about oh maybe I can do the two layer with the wafer to wafer bonding two layer wafer to wer as a pair then they use the micro bond connect those hybrid bonding so that's we so called

the hybrid hybrid bonding so I think the people start to think about uh with the more staking challenge how we can bring the advantage from both hybrid bonding and the microbond merge together I think right now we are still in the R&D phase

but I'm very excited to see that happen because that will be the easier the bridge lead us from the microbond to hybrid bonding.

>> Let's go back a little bit. You

mentioned co-ackaged optics.

>> C-acked optics bring in the same issues that you start dealing with in DRAM which is they are incredibly heat sensitive.

>> How do you deal with that in a really tight package where this stuff is all going to be bundled together. It's

what's what's your neighbor? How much

heat are they generating versus does this work by itself? I would say the coal packaging is one of the way to uh reduce the thermal effect again because we are thinking about if we always rely

on the electron to transmit our data we can image how much heat will generate right so we are talking about a couple different cooling technology like the water cooling mechanical cooling but I

do believe the coging will reduce a lot of the transmission heat actually that can bring down all the thermal effect across the overall package component even the system component so that's why

Today I also want to talk about what is the new challenge we see from the copy.

It's not about the thermal it's more about we are kind of a combined traditional optical uh technology into the semiconductor and we do see very different structure just design uh for

the optics uh packaging. I think that will be very interesting topic to talk about.

>> Is it going to be pluggable or is it going to be completely built into the design?

>> Uh I think in the market right now we are talking about a couple different generation for the co-patch. Sometimes

it's still separate, sometimes the building design, right? So in my opinion, I see the tier one uh leading customer and the AI company, they are doing the merge design. So I would say

the majority I feel like we'll start with the merge design because that can really bring the benefit combined with the the current AI packaging with the copy. I believe that will be the trend

copy. I believe that will be the trend and actually that is happen right now.

>> So the competition among the HBM vendors must be very intense right now.

>> That's true. And I think I can also share one information with you is that in the past our customer told us their cycle time is about two years per generation. So that means we still have

generation. So that means we still have the one year to study the problem and another six months to do the technology implementation. Then we release the

implementation. Then we release the production. But guess what? Right now

production. But guess what? Right now

they already reduce the cycle time to the one year. So that changed the whole scope because in the past we have the one year to study but no now one year including the R&D study pyong release

that caused a lot of the stress but I think that is the also demonstrate that the demand for the AI is really uh pushing the technology ination a lot and actually I'm very happy to see that sh happen as well.

>> What happens on the inspection side that's really where you're coming into this market right?

>> So I think speaking of the inspection uh let me uh use the whiteboard to explain a little bit. So because when we talk about the microbump the stacking height actually the most important will be the

CMP because we already talk about the all the dice become shrinking and shrinking and also dimension become smaller. So that means the all the via

smaller. So that means the all the via we want to do will become very tiny and as you can imagine [Music]

from mechanism but the challenge is that you can see this is very tiny. So in the past if we are talking about a 20 micron via with the one micron defect maybe

that doesn't matter because it's still away behind the process control window but you can think about once shrink down to the 10 micron one micron become the 10 pro 10% that is perfectly heat to the

process control window that means the one micron defect become matter. So

that's why we see more and more charge for the dent and the comma. This will

indicate the process variation and the sound escalation during the CMP process.

But in the past we do not have a very good uh technology including the sulfate to detect even distinguish these two type of the defect. I think that is the main challenge.

>> So you either have to get your process absolutely right or you need to add a lot of redundancy in here. Right.

>> Let that's true. So let's talk about this one because I think so let's back to the defense question. I still

remember at the beginning we are talking about like the thousand defect per wafer. So maybe the DOI is the 100. So

wafer. So maybe the DOI is the 100. So

we just need to reduce like the uh 10% of the nuisance defect. But right now in order to see this kind of tiny defect we are inspection like the 100,000 w defect

per waiver. Then that mean a nuisance

per waiver. Then that mean a nuisance become 90%. So how we can reduce the

become 90%. So how we can reduce the redundant defay that is the key and also we cannot spend too much time just on the nuisance defect. Right? So that's

why back to my original statement why we want to introduce the AI to enable the next gen AI because there are so many redundant data and we need to find a way to very smart to fill that out at once

otherwise we will take forever to do the inspection and that would not feed into the HBN environment for sure.

>> What about diwarpage? Obviously the

these things are under pressure. They've

got stresses that they didn't have before. The more layers you add, the

before. The more layers you add, the more stresses you add, the more heat you add, the more the stresses increase as well. And also that because it's so

well. And also that because it's so small it's it's going to be very concentrated a very small area.

>> That's correct. I think the dwarage is actually become more and more critical and the challenge for the high staking layer because as we can image if we sink down the second wafer it's easier to get

a wage right. So in the past we only see like the 20 micron wage 50 micron wobbage. Now what we are seeing 200

wobbage. Now what we are seeing 200 micron wobbage per die label. So you can image if we have the 200 micron wobbage with the 16 high we already out of the

semi standard. So that's why how to

semi standard. So that's why how to control the dwage and even find a way to for example like the pick and place the good wage combination. I think that is the key. So that's why we also have the

the key. So that's why we also have the technology to uh ensure we can measure the dwage on frame because people it's easy to measure the wage on wafer phone

but after that singulation actually it's very difficult. So that's why we

very difficult. So that's why we developed a new technology can inspect the DWage after the sewing. I think that is the key to enable the 20 high and above technology.

>> And what you're talking about is these chips are so small that by the time you take a look at them it looks planer completely even but it really isn't right.

>> Oh that's correct. So that's why uh I think um the challenge is that because we put the more VR together and as you can imagine the stress is just come together right and also send down the

wafer so that's why it's so difficult to control and I think right now we are still working with the customer so dwage is always from stress but how we can reduce the stress from the different

perspective for example I can give you one example right now we are also doing a lot of the H and backside inspection for the HBA why because actually there's a lot of the tiny stress from the edge

and even from the back side because when we send down the wafer we have to put the wafer on the carrier. So all the different component actually will be the contributor for the stress itself. So

it's not just about how we can make the uh D more flat. It's all about knowing all the different charger across the process and save the WPG issue tiny tiny by the different process that I think that is the key.

>> Damon Sai thanks for a great explanation. woke up.

explanation. woke up.